Contractual Defect Density Guarantee Structures across Secondary Foundry Wafer Supply Agreements
Effective defect guarantee structures map precise inspection recipes and mathematical yield models directly to gross-to-net credit adjustment formulas.
Baseline D0 Limits
Meaning
Maximum permissible defect counts per unit area of a silicon wafer establish the baseline for yield expectations in semiconductor fabrication. Wafer suppliers and foundry customers write baseline d0 limits into their master purchase agreements to define the boundaries of acceptable material quality before processing begins. If the incoming wafer defect density exceeds these boundaries, the material is rejected before it enters the expensive lithography steps.
This specification protects the buyer from sub-surface anomalies that would otherwise destroy chip yields. When agreements are negotiated, these thresholds are locked to prevent the supplier from delivering poorer grades during periods of high demand.
Commercial Allocation
Channel agreements distribute the risk of early-stage yield losses by pinning the responsibility to the wafer manufacturer. If wafer lots breach the baseline d0 limits, the manufacturer must replace the silicon or credit the buyer for the defective batch. Buyers typically verify these limits during incoming quality inspection to avoid running wafers through high-temperature steps where return rights are lost.
Defect Liability
Pricing models for raw silicon rely directly on the tightness of these quality boundaries. Tightening the baseline d0 limits pushes the list price up due to the lower yields experienced by the silicon crystal puller. Contracts usually include a sliding scale where a lower d0 value commands a premium.
Settlement Protocol
Disputes over wafer quality are resolved through independent metrology audits specified in the supply contract. These provisions prevent the supplier from disputing the buyer’s internal yield measurements. A neutral third-party laboratory runs the verification if the two parties reach an impasse.