Meaning
Recovery methodology for multi-core processors that involves selling chips with defective cores as lower-tier components. Manufacturers utilize core harvesting to salvage value from processors that would otherwise be discarded due to localized defects. By disabling non-functional cores and fusing the chip to a lower specification, the company maintains a higher effective yield across the wafer.
This practice is common in high-performance computing and consumer electronics where die sizes are large and defect probabilities are elevated.
Product Tiering
Segmentation of a single silicon design into multiple market stock-keeping units depends on functional core counts. Through core harvesting, a ten-core design that fails testing on two cores becomes an eight-core product sold at a different price point. This allows the manufacturer to address various market segments with a single mask set.
Buyers receive a product that meets all specifications for the lower tier despite its origin as a higher-end component.
Binning Logic
Technical sorting of parts occurs during the final test phase to determine the maximum stable configuration. The process of core harvesting requires precise identification of which cores meet performance targets and which must be permanently disabled. Electrical fuses or software locks ensure that the disabled cores cannot be accessed or cause power leakage during operation.
This logic ensures that the harvested product behaves identically to a natively designed lower-core chip. Automated test equipment applies specific patterns to verify that the remaining cores interact correctly with the shared memory and input systems. Successful verification permits the unit to enter the distribution channel as a certified lower-tier part.
Value Recovery
Financial impact of salvaging partially functional silicon reduces the average cost per good die. Without core harvesting, the manufacturer would face much higher waste costs on large-area chips. The recovered revenue from these lower-tier parts offsets the research and development expenses associated with complex architectures.
Profitability in the semiconductor industry often relies on the efficiency of this salvage process.