Meaning
Individual bare semiconductor chips that have undergone rigorous functional testing and burn-in screening to achieve parity with fully packaged integrated circuits constitute pre-assembly certified silicon. A known good die provides microelectronics assemblers with verified functional components before they are bonded into multi-chip modules, system-in-package solutions or stacked three-dimensional integrated architectures. The boundaries of this term encompass bare die testing protocols and bare substrate screening, terminating once components are encapsulated inside protective plastic, ceramic or metallic chip packages.
Yield Compounding
Packaging multiple bare die into single modular assemblies creates exponential yield loss if individual sub-components carry undetected manufacturing defects. A module containing eight unverified die with individual ninety-percent survival rates produces a final assembled package yield below forty-four percent, destroying commercial margins. Sourcing verified known good die guarantees that multi-chip packaging yields remain commercially viable, preventing the costly scrapping of expensive substrate materials and functional companion silicon.
Higher initial unit die procurement costs are offset by dramatic reductions in finished package scrap rates.
Testing Architecture
Verifying bare silicon requires specialized probe cards and temporary contact carriers that simulate full thermal and electrical packaging stresses without damaging delicate microscopic contact pads. Foundries subject individual die to full-speed functional vectors, high-voltage stress screening and dynamic burn-in testing while still in wafer format or loose die carriers. Thermal dissipation during high-power bare die probe testing presents physical constraints that demand active cryogenic cooling or liquid chilled probe heads.
Temporary contact technologies leave minimal probe marks, preserving pad integrity for subsequent wire bonding, copper pillar attachment or micro-bump soldering.
Commercial Risk
Procurement contracts define precise defective parts per million metrics alongside liability terms covering catastrophic module-level failures. Standard packaged chip warranties cover simple part replacement, whereas bare die supply agreements governing high-density multi-chip modules require explicit negotiated liabilities for down-assembly damage. Dispute resolution centers on determining whether packaging failures stem from latent semiconductor defects or thermomechanical damage induced during downstream mounting processes.
Foundries charge substantial premiums for fully tested bare die to cover specialized probe tooling investments and longer test cell retention times.
