Meaning
The financial dynamics that determine the cost per transistor and the required manufacturing volume for a specific semiconductor lithography generation. Analysis of process node economics helps chip designers decide whether to migrate to a smaller node, like five nanometer, or remain on a mature, lower-cost planar node. The decision involves balancing the massive upfront mask set costs against the lower variable cost per wafer of advanced nodes.
Capital Intensity
Building and equipping a modern fabrication facility to run advanced lithography processes requires billions of dollars in capital expenditure. These process node economics dictate that only a few high-volume chips, such as mobile processors, can generate enough sales to amortize the multi-million-dollar cost of a single mask set. For industrial and automotive applications with lower total volumes, mature nodes remain the most profitable choice because their tooling costs are fully depreciated.
This barrier protects established suppliers from new entrants.
Yield Curve
The profitability of a new manufacturing process is highly dependent on how quickly the foundry can reduce defects and increase the percentage of functional dies per wafer. Process node economics assume that early production runs will have low yields, which are compensated for by high initial average selling prices. As the process matures and yield improves, the cost per chip drops, allowing the supplier to lower prices and enter broader market segments.
Supply Strategy
Distributing silicon built on mature nodes offers long-term supply stability but limits the potential for performance upgrades. Understanding process node economics prevents product managers from designing chips on nodes that are scheduled for decommission or that suffer from chronic capacity shortages. It ensures that the selected technology remains viable for the lifetime of the customer’s product.