Semiconductor Wafer Yield Modeling for Industrial Processors
Wafer yield modeling maps physical defect density and spatial clustering to net functional die costs, setting commercial terms for advanced foundry contracts.
Electrical Die Sorting
Meaning
Automated testing process conducted at the wafer level to identify functional integrated circuits before packaging. During electrical die sorting, a probe card makes physical contact with the bond pads of each circuit to verify its performance against the design specifications. Units that fail these tests are marked in a digital map so they can be bypassed during the assembly phase.
This step is the first point where the manufacturer gains a clear view of the actual yield of a production lot.
Probing Sequence
Mechanical alignment of the test equipment must be precise to avoid damaging the delicate silicon surface. The electrical die sorting routine moves from one die to the next in a pre-defined path to minimize the total test time. High-speed testers measure parameters such as voltage levels, timing and power consumption.
Any unit falling outside the acceptable range is categorized into specific bins based on the nature of the failure.
Map Generation
Digital documentation of the test results guides the automated pick and place machines during packaging. Data from electrical die sorting is stored in a wafer map file that travels with the lot through the remaining manufacturing steps. This file ensures that only the good dies are encapsulated in expensive ceramic or plastic packages.
It also provides a historical record that engineers use to trace yield losses back to specific steps in the fabrication process. Advanced mapping techniques can even predict the reliability of dies located near clusters of failures. This information allows for the exclusion of dies that might pass initial tests but are likely to fail in the field.
Result Outcome
Financial settlement between the foundry and the customer often depends on the results of this testing stage. Under many contracts, the electrical die sorting results determine the final payment amount for a wafer lot. This creates a clear boundary where the risk of manufacturing defects is assessed and assigned.
Efficient sorting reduces the cost of assembly by ensuring that resources are not wasted on defective silicon.