Meaning
Spatial mismatch between successive patterned layers on a semiconductor wafer caused by inaccuracies in the photolithography exposure stage. Manufacturing contracts define stage overlay error limits to ensure that different metal and transistor layers align correctly to form functional circuits. If the layers are misaligned, the chip will fail due to short circuits or open connections.
This metric is a key indicator of scanner precision and cleanroom control.
Alignment Tolerance
Complex designs require dozens of layered exposures, and each must line up with sub-nanometer precision. A high level of stage overlay error degrades the contact areas between layers, reducing the cross-sectional area of vias and metal lines. This reduction increases electrical resistance and can lead to premature chip failure.
Consequently, foundries establish tight tolerance windows that scanners must meet to continue production.
Lithographic Variance
Mechanical drift and thermal expansion of the wafer stage during exposure contribute to positioning errors. As the stage moves rapidly from field to field, minute vibrations disrupt the alignment of the projected image with the existing patterns on the wafer. Engineers monitor this variance using specialized metrology tools that measure test keys on the wafer.
This monitoring allows the system to apply real-time feedback corrections.
Pricing Adjustment
Distribution agreements for high-yield wafer production incorporate performance-based penalties tied to stage registration accuracy. When a batch exhibits high stage overlay error, the foundry must either scrap the wafers or offer them at a steep discount to offset the buyer’s expected yield loss. If the alignment is outside the specified contract limits, the buyer has the right to reject the entire shipment.
This commercial pressure forces foundries to dedicate their best-performing lithography tools to their most critical customer accounts, securing high margins for both parties.