Evaluating Requalification and Layout Expenses in Wide Bandgap Power Conversions
Evaluating wide bandgap power conversions requires balancing switch price premiums and board redesign costs against magnetic component and enclosure savings.
Stray Inductance Limits
Meaning
Maximum acceptable bounds for parasitic inductance in high-speed electrical circuits dictate the safety margin against voltage overshoot. Component specifiers establish stray inductance limits to protect sensitive power semiconductors from destructive overvoltage conditions. Adhering to these boundaries ensures the circuit remains stable under rapid switching transients.
Packaging Constraint
Layout optimization represents the main method to keep parasitic inductances below the established limits. Modern packaging styles use planar busbars and Kelvin source connections to minimize the inductance of internal terminals. Designing within the stray inductance limits reduces the need for expensive snubber circuits.
Quality Standard
Manufacturing tolerances in semiconductor assembly can cause variations in the internal inductance of the modules. Standardized testing must verify that each production batch complies with the specified stray inductance limits before packaging. Reliable measurements protect the supplier from delivering inconsistent parts that could fail in the field.
Supply Agreement
Procurement contracts often reference these electrical limits as a condition for product acceptance. If a supplier fails to maintain the stray inductance limits, the buyer may invoke indemnity clauses to cover the cost of field failures. These strict contract terms incentivize the supplier to implement rigorous testing protocols and maintain high manufacturing standards.
Detailed agreements also outline the testing methods used to verify compliance, which prevents disputes between the engineering teams of both companies and ensures a smooth supply chain flow.